Scan test architectures for digital board testers

Publisher Website

4 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/test.1990.114036

Abstract

No abstract available

Keywords

This publication has 2 references indexed in Scilit:

Testing conventional logic and memory clusters using boundary scan devices as virtual ATE channels
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
Interconnect testing of boards with partial boundary scan
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002