Interconnect testing of boards with partial boundary scan
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- A new framework for analyzing test generation and diagnosis algorithms for wiring interconnectsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Testing and diagnosis of interconnects using boundary scan architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Scan test architectures for digital board testersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Electronic Chip-in-Place TestPublished by Association for Computing Machinery (ACM) ,1982