Testing and diagnosis of interconnects using boundary scan architecture

6 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 126-137
https://doi.org/10.1109/test.1988.207790

Abstract

A built-in self-test of interconnects based on boundary scan architecture is described. Detection and diagnosis schemes are proposed which provide minimal-size test vector sets. I/O scan chains order independent test vector sets and walking sequences. Properties like ease of test vector generation, structure-independent detection and diagnosis, and local response compaction have made the developed schemes suitable for built-in-self-test implementation. An example board-interconnect test session is described using one of the proposed schemes.<>

Keywords

This publication has 4 references indexed in Scilit:

Macro Testing: Unifying IC And Board Test
IEEE Design & Test of Computers, 1986
On driving many long wires in a VLSI layout
Journal of the ACM, 1986
In-Circuit Testing
Published by Springer Nature ,1985
Testing for Faults in Wiring Networks
IEEE Transactions on Computers, 1974