Transistor analogs of emergent iono‐neuronal dynamics

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Abstract
Neuromorphic analog metal‐oxide‐silicon (MOS) transistor circuits promise compact, low‐power, and high‐speed emulations of iono‐neuronal dynamics orders‐of‐magnitude faster than digital simulation. However, their inherently limited input voltage dynamic range vs power consumption and silicon die area tradeoffs makes them highly sensitive to transistor mismatch due to fabrication inaccuracy, device noise, and other nonidealities. This limitation precludes robust analog very‐large‐scale‐integration (aVLSI) circuits implementation of emergent iono‐neuronal dynamics computations beyond simple spiking with limited ion channel dynamics. Here we present versatile neuromorphic analog building‐block circuits that afford near‐maximum voltage dynamic range operating within the low‐power MOS transistor weak‐inversion regime which is ideal for aVLSI implementation or implantable biomimetic device applications. The fabricated microchip allowed robust realization of dynamic iono‐neuronal computations such as coincidence...