An analog MOS implementation of the synaptic weights for feedforward/feedback neural nets

13 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 1, 1016-1019
https://doi.org/10.1109/mwscas.1989.102026

Abstract

An all-MOS realization of the linear synaptic weight for neural nets is described. The realization is achieved via an adaptation of continuous-time analog multipliers where the weights are assigned as positive or negative voltage levels. Using only a single newly designed CMOS operational amplifiers, each analog multiplier is capable of realizing the scalar product Sigma W/sub ij/X/sub j/, j=1, . . ., n, and i is fixed, where X/sub j/ is an external input or an output of neuron j and W/sub ij/ is the externally assignable positive or negative weight. The artificial neural network would then be realized by double inverters interconnected to the designed analog multipliers. Two designs are described, and the resulting (SPICE) simulations of all-MOS multiplier circuits for feedforward neural networks are presented.

Keywords

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