Spin-based logic in semiconductors for reconfigurable large-scale circuits

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Abstract
This paper reports a theoretical design that is a conceptual step forward; spin accumulation is used as the basis of a semiconductor computer circuit rather than flow of spin. A logic gate in this design consists of five magnetic leads on top of a semiconductor layer and is found to perform fast logic operations. The idea is further developed by demonstrating the capability to interconnect a large number of gates. Research in semiconductor spintronics aims to extend the scope of conventional electronics by using the spin degree of freedom of an electron in addition to its charge1. Significant scientific advances in this area have been reported, such as the development of diluted ferromagnetic semiconductors2,3, spin injection into semiconductors from ferromagnetic metals4,5,6,7,8 and discoveries of new physical phenomena involving electron spin9,10. Yet no viable means of developing spintronics in semiconductors has been presented. Here we report a theoretical design that is a conceptual step forward—spin accumulation is used as the basis of a semiconductor computer circuit. Although the giant magnetoresistance effect in metals11,12 has already been commercially exploited, it does not extend to semiconductor/ferromagnet systems, because the effect is too weak for logic operations. We overcome this obstacle by using spin accumulation rather than spin flow13,14,15. The basic element in our design is a logic gate that consists of a semiconductor structure with multiple magnetic contacts; this serves to perform fast and reprogrammable logic operations in a noisy, room-temperature environment. We then introduce a method to interconnect a large number of these gates to form a ‘spin computer’. As the shrinking of conventional complementary metal-oxide–semiconductor (CMOS) transistors reaches its intrinsic limit, greater computational capability will mean an increase in both circuit area and power dissipation. Our spin-based approach may provide wide margins for further scaling and also greater computational capability per gate.