Electrical characteristics of scaled CMOSFET's with source/drain regions fabricated by 7° and 0° tilt-angle implantations
- 1 January 1995
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 42 (1) , 70-77
- https://doi.org/10.1109/16.370033
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- Narrow-width effects of shallow trench-isolated CMOS with n/sup +/-polysilicon gateIEEE Transactions on Electron Devices, 1989
- A practical trench isolation technology with a novel planarization processPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- A new degradation mechanism of current drivability and reliability of asymmetrical LDDMOSFET'sPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- Channeling of Phosphorous Ions in SiliconApplied Physics Letters, 1972