0.18 μm metal gate fully-depleted SOI MOSFETs for advanced CMOS applications
- 20 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
We report here for the first time a 0.18 /spl mu/m fully-depleted SOI process with PVD TiN metal gate. As midgap work function metal gate and very light channel doping were used, threshold voltage can be easily controlled in /spl plusmn/300 mV to /spl plusmn/500 mV range and on-wafer V/sub t/ variation was only about /spl plusmn/5 mV. Short channel effects can be further improved when silicon film thickness is thinner than 300 /spl Aring/. Subthreshold slope was kept below 75 mV/dec even for subnominal devices and V/sub t/ roll-offs for both N- and P-MOSFETs were very small.Keywords
This publication has 3 references indexed in Scilit:
- Tantalum-gate thin-film SOI nMOS and pMOS for low-power applicationsIEEE Transactions on Electron Devices, 1997
- 0.18-μm fully-depleted silicon-on-insulator MOSFET'sIEEE Electron Device Letters, 1997
- Silicon-on-Insulator Technology: Materials to VLSIPublished by Springer Nature ,1997