Application of a Junction Field Effect Transistor Structure to a Low Loss Diode

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Abstract
A novel low loss diode with junction grids has been proposed. Numerical simulations reveal that, for this diode, designing a submicron grid width improves the tradeoff characteristics between the forward voltage drop and the leakage current, leading to characteristics superior to those of the Schottky barrier diode. The introduction of a lateral silicon-on-insulator (SOI) structure into the proposed diode is attractive for achieving such a small grid width. The simulation also demonstrates design methods for channel doping and thickness of the buried oxide layer in the SOI diode.