Delay computation in combinational logic circuits: theory and algorithms
- 10 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- The effects of false paths in high-level synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Path sensitization in critical path problemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Integrating Functional and Temporal Domains in Logic DesignPublished by Springer Nature ,1991
- Diagnosis of Automata Failures: A Calculus and a MethodIBM Journal of Research and Development, 1966
- On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic NetsIEEE Transactions on Electronic Computers, 1966