An approach to fast hierarchical fault simulation
- 6 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 698-703
- https://doi.org/10.1109/dac.1988.14845
Abstract
We present an approach to hierarchical fault simulation which generates several simulation-models of one circuit and carries out simulation for each. Fault insertion and simulation-model generation is done automatically. Switch-level simulation which utilizes look-up tables is as fast as gate-level simulation. Experimental results show that using behavioral description and switch-level truth tables is effective to improve simulation speed.Keywords
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