Secure random number generation using chaotic circuits

1 September 1990

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems

Vol. 37 (9) , 1157-1164
https://doi.org/10.1109/31.57604

Abstract

The authors suggest a class of circuits for generating secure pseudo-random numbers and estimate the security of these generators from the information loss property of chaotic systems. For a generator implemented using a chaotic DPLL (digital phase-locked loop), two important cases are considered: (1) given no prior information concerning the initial conditions of a continuously running circuit, the length of time one should wait after taking a bit before one can securely take another bit is established; and (2) given knowledge of the initial conditions at startup (up to measurement and noise uncertainty), the length of time one should wait before starting the bit sampling is shown.<>

Keywords

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