Instruction fetch mechanisms for VLIW architectures with compressed encodings
- 24 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
VLIW architectures use very wide instruction words in conjunction with high bandwidth to the instruction cache to achieve multiple instruction issue. This report uses the TINKER experimental testbed to examine instruction fetch and instruction cache mechanisms for VLIWs. A compressed instruction encoding for VLIWs is defined and a classification scheme for i-fetch hardware for such an encoding is introduced. Several interesting cache and i-fetch organizations are described and evaluated through trace-driven simulations. A new i-fetch mechanism using a silo cache is found to have the best performance.Keywords
This publication has 16 references indexed in Scilit:
- An architecture for high instruction level parallelismPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- The difference-bit cacheACM SIGARCH Computer Architecture News, 1996
- Tuning the Pentium Pro microarchitectureIEEE Micro, 1996
- Developing the AMD-K5 architectureIEEE Micro, 1996
- The superblock: An effective technique for VLIW and superscalar compilationThe Journal of Supercomputing, 1993
- The cydra 5 minisupercomputer: Architecture and implementationThe Journal of Supercomputing, 1993
- The multiflow trace scheduling compilerThe Journal of Supercomputing, 1993
- Hardware Support For Large Atomic Units in Dynamically Scheduled MachinesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- Branch folding in the CRISP microprocessor: reducing branch delay to zeroPublished by Association for Computing Machinery (ACM) ,1987
- Experimental evaluation of on-chip microprocessor cache memoriesACM SIGARCH Computer Architecture News, 1984