A simple denotational semantics, proof theory and a validation condition generator for unit-delay VHDL
- 1 August 1995
- journal article
- research article
- Published by Springer Nature in Formal Methods in System Design
- Vol. 7 (1-2) , 27-51
- https://doi.org/10.1007/bf01383872
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- Toward a formal semantics of IEEE Std. VHDL 1076Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Clean formal semantics for VHDLPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Formal Semantics for VHDLPublished by Springer Nature ,1995
- An axiomatic basis for computer programmingCommunications of the ACM, 1969