Code Constructions for Error Control in Byte Organized Memory Systems
- 1 June 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-32 (6) , 535-542
- https://doi.org/10.1109/TC.1983.1676275
Abstract
Error correcting codes, such as Hamming codes, have been used successfully to correct errors arising from failures in computer memories. Failure of a chip or card can cause errors which exceed the capabilities of these codes. We construct codes which detect any byte error and correct such errors if they are single random errors. A subclass of the codes developed is shown to have the additional capability of detecting double errors. These codes are intended for use when data are packaged on a byte per chip or a byte per card basis. The codes require fewer check bits than any previously known to the authors except when the byte length or number of bytes is small.Keywords
This publication has 6 references indexed in Scilit:
- A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital SystemsIEEE Transactions on Computers, 1978
- Measurement and Generation of Error Correcting Codes for Package FailuresIEEE Transactions on Computers, 1978
- Error-Correcting Codes for Byte-Organized Arithmetic ProcessorsIEEE Transactions on Computers, 1975
- A General Class of Maximal Codes ror Computer ApplicationsIEEE Transactions on Computers, 1972
- Error Correction in High-Speed ArithmeticIEEE Transactions on Computers, 1972
- On codes derivable from the tensor product of check matricesIEEE Transactions on Information Theory, 1965