Error Correction in High-Speed Arithmetic

1 May 1972

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers

Vol. C-21 (5) , 433-438
https://doi.org/10.1109/T-C.1972.223538

Abstract

In high-speed multipliers, multiplication is activated by processing a group of bits in parallel. As a result, any defects in circuitry produce possible errors in positions that are separated by fixed periods. A class of codes for the correction of such iterative error patterns resulting from a single fault is presented in this paper. A decoding algorithm together with a simple implementation scheme is also discussed.

Keywords

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