A 20MHz 32b pipelined CMOS image processor

23 March 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 102-103
https://doi.org/10.1109/isscc.1986.1156909

Abstract

A 32b image processor with writable control stores that can process a 1024-point complex FFT in 1ms, has been developed. This paper will report on features which include fabrication in 1.2μm N-well CMOS, use of double layer metal technology and the integration of 170K transistors. Dissipation is 750mw at 5V.

Keywords

CMOS PROCESS
SIGNAL PROCESSING
CLOCKS
BIOMEDICAL ENGINEERING
PIPELINES
READ-WRITE MEMORY
REGISTERS
CIRCUIT TESTING
ELECTRONICS PACKAGING
SEMICONDUCTOR DEVICES

This publication has 2 references indexed in Scilit:

A VLSI image pipeline processor
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1984
An image signal processor
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1983