Chip scale package (CSP) "a lightly dressed LSI chip"
- 17 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 76, 169-176
- https://doi.org/10.1109/iemt.1994.404671
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- Ball Grid Array (BGA): The New Standard For High I/O Surface Mount PackagesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Volume production of unique plastic surface-mount modules for the IBM 80-ns 1-Mbit DRAM chip by area wire bond techniquesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Flip-chip on FR-4 integrated circuit packagingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Dissolution of Solid Copper into Molten Tin-Lead Alloys under Static ConditionsTransactions of the Japan Institute of Metals, 1980
- Reliability of Controlled Collapse InterconnectionsIBM Journal of Research and Development, 1969
- Thermal Stress and Low Cycle FatigueJournal of Applied Mechanics, 1966