Yield implications and scaling laws for submicrometer devices
- 1 May 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Semiconductor Manufacturing
- Vol. 1 (2) , 49-61
- https://doi.org/10.1109/66.4374
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- VLSI Yield Prediction and Estimation: A Unified FrameworkIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- Role of defect size distribution in yield modelingIEEE Transactions on Electron Devices, 1985
- Defect size variations and their effect on the critical area of VLSI devicesIEEE Journal of Solid-State Circuits, 1985
- Modeling the critical area in yield forecastsIEEE Journal of Solid-State Circuits, 1985
- Modeling of Lithography Related Yield Losses for CAD of VLSI CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- Modeling of defects in integrated circuit photolithographic patternsIBM Journal of Research and Development, 1984
- Modeling of Integrated Circuit Defect SensitivitiesIBM Journal of Research and Development, 1983