Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits
- 1 July 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 4 (3) , 166-177
- https://doi.org/10.1109/tcad.1985.1270112
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- VLASIC: A Catastrophic Fault Yield Simulator for Integrated CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Sources of failures and yield improvement for VLSIProceedings of the IEEE, 1984
- Modeling of Integrated Circuit Defect SensitivitiesIBM Journal of Research and Development, 1983
- Integrated circuit yield statisticsProceedings of the IEEE, 1983
- Yield estimation model for VLSI artwork evaluationElectronics Letters, 1983
- Determining IC layout rules for cost minimizationIEEE Journal of Solid-State Circuits, 1981