Determining IC layout rules for cost minimization

Abstract

A general and practical method for design rule optimization (i.e. IC cost minimization) is presented, and then demonstrated in detail for specific examples. The optimum design rules are shown to be insensitive to chip area or defect density, but strongly dependent on tolerance sizes, number of masking levels, and to a parameter which will be defined as the `area overhead factor'. Throughout the development, limitations and assumptions are thoroughly discussed, with the overall result that the method is shown to be immediately useful for arbitrary, but well characterized, fabrication processes and lithography equipment.

Keywords

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