A four-point electrical measurement technique for characterizing mask superposition errors on semiconductor wafers
- 1 August 1978
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 13 (4) , 436-444
- https://doi.org/10.1109/jssc.1978.1051074
Abstract
Data are obtained using a microelectronic van der Pauw resistor structure in conjunction with automated test, computing, and graphic display equipment. Computer-drawn vector displacement maps, equivalue contour maps, and histograms are used to display the data in a format which assists in the interpretation of sources of MSE. A six-parameter model which takes into account mask translation, rotation, and expansion is shown to fit successfully the data obtained from test wafers masked using conventional alignment equipment. A comparative evaluation of the performance of a group of aligners used for manufacturing integrated circuits is given, and an investigation of the consequences of masking silicon wafers which have been subjected to high-temperature processing is performed.Keywords
This publication has 5 references indexed in Scilit:
- A van der Pauw resistor structure for determining mask superposition errors on semiconductor slicesSolid-State Electronics, 1978
- Effect Of Plastic Deformation Of Silicon Wafers On OverlayPublished by SPIE-Intl Soc Optical Eng ,1977
- Four‐Point Sheet Resistance Measurements of Semiconductor Doping UniformityJournal of the Electrochemical Society, 1977
- A comparison of electrical and visual alignment test structures for evaluating photomask alignment in integrated circuit manufacturingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1977
- Analysis of superposition errors in wafer fabricationMicroelectronics Reliability, 1977