A fast VLSI adder architecture
- 1 May 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 27 (5) , 761-767
- https://doi.org/10.1109/4.133165
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- High-speed VLSI arithmetic processor architectures using hybrid number representationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- High-speed VLSI arithmetic processor architectures using hybrid number representationJournal of Signal Processing Systems, 1992
- A new carry-free division algorithm and its application to a single-chip 1024-b RSA processorIEEE Journal of Solid-State Circuits, 1990
- A CMOS floating point multiplierIEEE Journal of Solid-State Circuits, 1984
- A Regular Layout for Parallel AddersIEEE Transactions on Computers, 1982
- Signed-Digit Numbe Representations for Fast Parallel ArithmeticIEEE Transactions on Electronic Computers, 1961