High-speed VLSI arithmetic processor architectures using hybrid number representation
- 10 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 9 references indexed in Scilit:
- A systematic approach for design of digit-serial signal processing architecturesIEEE Transactions on Circuits and Systems, 1991
- A new carry-free division algorithm and its application to a single-chip 1024-b RSA processorIEEE Journal of Solid-State Circuits, 1990
- Concurrent cellular VLSI adaptive filter architecturesIEEE Transactions on Circuits and Systems, 1987
- Design of high speed MOS multiplier and divider using redundant binary representationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- A 70-MHz 8-bit×8-bit parallel pipelined multiplier in 2.5-μm CMOSIEEE Journal of Solid-State Circuits, 1986
- A Pipelined 330-MHz MultiplierIEEE Journal of Solid-State Circuits, 1986
- A division algorithm with prediction of quotient digitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- Signed-Digit Numbe Representations for Fast Parallel ArithmeticIEEE Transactions on Electronic Computers, 1961
- A New Class of Digital Division MethodsIRE Transactions on Electronic Computers, 1958