A 70-MHz 8-bit×8-bit parallel pipelined multiplier in 2.5-μm CMOS

This publication has 11 references indexed in Scilit:

• The systematic exploration of pipelined array multiplier performance
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
• A 16 bitx16 bit pipelined multiplier macrocell
  IEEE Journal of Solid-State Circuits, 1985
• A design by example regular structure generator
  Published by Association for Computing Machinery (ACM) ,1985
• Completely-pipelined architectures for digital signal processing
  IEEE Transactions on Acoustics, Speech, and Signal Processing, 1983
• A VLSI layout for a pipelined Dadda multiplier
  ACM Transactions on Computer Systems, 1983
• A high-speed LSI GaAs 8x8 bit parallel multiplier
  IEEE Journal of Solid-State Circuits, 1982
• Completely iterative, pipelined multiplier array suitable for VLSI
  IEE Proceedings G (Electronic Circuits and Systems), 1982
• MULGA-An Interactive Symbolic Layout System for the Design of Integrated Circuits
  Bell System Technical Journal, 1981
• Virtual Grid Symbolic Layout
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1981
• A Two's Complement Parallel Array Multiplication Algorithm
  IEEE Transactions on Computers, 1973