A high-speed LSI GaAs 8x8 bit parallel multiplier

Abstract

Multiplication is frequently the speed-limiting function in digital signal processing systems. High-speed hardware multiplier ICs can therefore greatly enhance the throughput and bandwidth of many digital systems. In this paper, the design, fabrication, and performance of GaAs parallel multipliers are discussed. The largest of these circuits, an 8/spl times/8 bit multiplier, has 1008 gates, and is by far the most complex GaAs IC demonstrated today. This multiplier forms the 16 bit product of two 8 bit input numbers in 5.25 ns. This corresponds to an equivalent gate propagation delay of 150 ps/gate. The power dissipation ranges between 0.6-2 mW/gate.

Keywords

This publication has 9 references indexed in Scilit:

Process evaluation test structures and measurement techniques for a planar GaAs digital IC technology
IEEE Transactions on Electron Devices, 1980
GaAs gigabit logic circuits using normally-off m.e.s.f.e.t.s
Electronics Letters, 1980
High-speed NMOS circuits made with X-ray lithography and reactive sputter etching
IEEE Electron Device Letters, 1980
Degradation mechanism of GaAs MESFET's
IEEE Transactions on Electron Devices, 1979
The prospects for ultrahigh-speed VLSI GaAs digital logic
IEEE Journal of Solid-State Circuits, 1979
1 /spl mu/m MOSFET VLSI technology. II. Device designs and characteristics for high-performance logic applications
IEEE Journal of Solid-State Circuits, 1979
SOS MESFET processing technology for microwave integrated circuits
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1979
Planar high yield GaAs IC processing techniques
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1979
Reliability Study of GaAs MESFET's
IEEE Transactions on Microwave Theory and Techniques, 1976