A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization
- 5 December 2005
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 40 (12) , 2633-2645
- https://doi.org/10.1109/jssc.2005.856584
Abstract
A 4.9-6.4-Gb/s two-level SerDes ASIC I/O core employing a four-tap feed-forward equalizer (FFE) in the transmitter and a five-tap decision-feedback equalizer (DFE) in the receiver has been designed in 0.13-/spl mu/m CMOS. The transmitter features a total jitter (TJ) of 35 ps p-p at 10/sup -12/ bit error rate (BER) and can output up to 1200 mVppd into a 100-/spl Omega/ differential load. Low jitter is achieved through the use of an LC-tank-based VCO/PLL system that achieves a typical random jitter of 0.6 ps over a phase noise integration range from 6 MHz to 3.2 GHz. The receiver features a variable-gain amplifier (VGA) with gain ranging from -6to +10dB in /spl sim/1dB steps, an analog peaking amplifier, and a continuously adapted DFE-based data slicer that uses a hybrid speculative/dynamic feedback architecture optimized for high-speed operation. The receiver system is designed to operate with a signal level ranging from 50 to 1200 mVppd. Error-free operation of the system has been demonstrated on lossy transmission line channels with over 32-dB loss at the Nyquist (1/2 Bd rate) frequency. The Tx/Rx pair with amortized PLL power consumes 290 mW of power from a 1.2-V supply while driving 600 mVppd and uses a die area of 0.79 mm/sup 2/.Keywords
This publication has 9 references indexed in Scilit:
- Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiverPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- An 8Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskewPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cellIEEE Journal of Solid-State Circuits, 2003
- An adaptive pam-4 5-Gb/s backplane transceiver in 0.25-μm CMOSIEEE Journal of Solid-State Circuits, 2003
- A 0.5-3.5 Gb/s low-power low-jitter serial data CMOS transceiverPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An adaptive cable equalizer for serial digital video rates to 400 Mb/sPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Design issues in CMOS differential LC oscillatorsIEEE Journal of Solid-State Circuits, 1999
- Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ±50 ps jitterIEEE Journal of Solid-State Circuits, 1995
- Techniques for high-speed implementation of nonlinear cancellationIEEE Journal on Selected Areas in Communications, 1991