Design And Testing Of SEU/ SEL Immune Memory And Logic Circuits In A Commercial Cmos Process

Publisher Website

24 August 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 51-55
https://doi.org/10.1109/redw.1993.700568

Abstract

No abstract available

Keywords

This publication has 2 references indexed in Scilit:

Low power SEU immune CMOS memory circuits
IEEE Transactions on Nuclear Science, 1992
SEU hardened memory cells for a CCSDS Reed-Solomon encoder
IEEE Transactions on Nuclear Science, 1991