Test generation in a parallel processing environment

Publisher Website

6 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/iccd.1988.25649

Abstract

No abstract available

Keywords

This publication has 4 references indexed in Scilit:

ON THE ACCELERATION OF TEST GENERATION ALGORlTHMS
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
Parallel Processing for CAD Applications
IEEE Design & Test of Computers, 1987
Effectiveness of heuristics measures for automatic test pattern generation
Published by Association for Computing Machinery (ACM) ,1986
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers, 1981