A gigabit MOS logic circuit with buried channel MOSFETs
- 1 October 1980
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 15 (5) , 809-816
- https://doi.org/10.1109/JSSC.1980.1051475
Abstract
An MOS frequency divider operating with gigabit clock rate has been realized to show the potential of MOS logic circuits for high-speed applications. The divider was constructed with buried channel MOSFETs as the basic elements. A master-slave flip-flop that was constructed with the enhancement/depletion type NAND gates was used for the divider. The basic gates were designed using full 1 /spl mu/m patterning rules. For the fabrication of these very fine circuits, photomasks made by an electron-beam system were applied and sputter etching was employed to form fine patterns such as the polysilicon gate and contact holes. The maximum counting frequency of 1.64 GHz and the shortest propagation delay time of 72.5 ps/gate with a fundamental gate were obtained.Keywords
This publication has 4 references indexed in Scilit:
- Gigabit electronics—A reviewProceedings of the IEEE, 1979
- Two-dimensional numerical analysis of normally-off type buried channel MOSFET'sPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- A normally-off type buried channel MOSFET for VLSI circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1978
- Sub-micron polysilicon Gate CMOS/SOS technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1978