Bit-Sequential Arithmetic for Parallel Processors
- 1 January 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-33 (1) , 7-20
- https://doi.org/10.1109/tc.1984.5009311
Abstract
A bit-sequential processing element with O(n) complexity is described, where n is the wordlength of the operands. The operations performed by the element are A * B + C * D, A/B, and √A. The operands are fixed point or floating point numbers with variable precision. The concept of semi-on-line algorithms is introduced. A processing element that uses semi-on-line algorithms produces a result δ clock cycles after the absorption of the n-bit operands, where δ is small compared to n. In the paper the processing element and the algorithms are described. A performance comparison between the bit-sequential processing element and conventional pipelined arithmetic units is given.Keywords
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