Realistic worst-case SPICE file extraction using BSIM3

Publisher Website

19 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/cicc.1995.518206

Abstract

No abstract available

Keywords

This publication has 3 references indexed in Scilit:

Realistic statistical worst-case simulations of VLSI circuits
IEEE Transactions on Semiconductor Manufacturing, 1991
A Methodology for Worst-Case Analysis of Integrated Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
Statistical modeling for efficient parametric yield estimation of MOS VLSI circuits
IEEE Transactions on Electron Devices, 1985