Branch prediction, instruction-window size, and cache size: performance trade-offs and simulation techniques
- 1 January 1999
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 48 (11) , 1260-1281
- https://doi.org/10.1109/12.811115
Abstract
No abstract availableThis publication has 43 references indexed in Scilit:
- Analysis techniques for predicated codePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Trace cache: a low latency approach to high bandwidth instruction fetchingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Load latency tolerance in dynamically scheduled processorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Accurate indirect branch predictionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Threaded multiple path executionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Design issues and tradeoffs for write buffersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Recovery requirements of branch prediction storage structures in the presence of mispredicted-path executionInternational Journal of Parallel Programming, 1997
- Alternative implementations of hybrid branch predictorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1995
- Limits on multiple instruction issueACM SIGARCH Computer Architecture News, 1989
- Accurate low-cost methods for performance evaluation of cache memory systemsIEEE Transactions on Computers, 1988