Generation of a Clock Pulse for Asynchronous Sequential Machines to Eliminate Critical Races
- 1 February 1971
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-20 (2) , 225-226
- https://doi.org/10.1109/t-c.1971.223219
Abstract
A circuit for generating a clock pulse for asynchronous circuits is given, and when used with transition sensitive flip-flops eliminates critical races for an arbitrary state assignment. Thus the minimum number of internal variables may be used. Furthermore, logic and sequential hazards will not affect the circuit performance.Keywords
This publication has 4 references indexed in Scilit:
- On Asynchronous Machines with Flip-FlopsIEEE Transactions on Computers, 1969
- Transition Logic Circuits and a Synthesis MethodIEEE Transactions on Computers, 1969
- Internal State Assignments for Asynchronous Sequential MachinesIEEE Transactions on Electronic Computers, 1966
- Hazard detection in combinational and sequential switching circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1964