Timing Influenced Layout Design
- 1 January 1985
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 124-130
- https://doi.org/10.1109/dac.1985.1585923
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- Chip Layout Optimization Using Critical Path WeightingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- Hierarchical Wire RoutingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983
- A Linear-Time Heuristic for Improving Network PartitionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- Timing Analysis of Computer HardwareIBM Journal of Research and Development, 1982