Chip Layout Optimization Using Critical Path Weighting
- 1 January 1984
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 0738100X,p. 133-136
- https://doi.org/10.1109/dac.1984.1585786
Abstract
A chip layout procedure for optimizing the performance of critical timing paths in a synchronous digital circuit is presented. The procedure uses the path analysis data produced by a static timing analysis program to generate weights for critical nets on clock and data paths. These weights are then used to bias automatic placement and routing in the layout program. This approach is shown to bring the performance of the chip significantly closer to that of an ideal layout which is assumed to have no delay due to routing between cells.Keywords
This publication has 3 references indexed in Scilit:
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