GSM 900/DCS 1800 fractional-N frequency synthesizer with very fast settling time

13 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 2 (0149645X) , 705-708
https://doi.org/10.1109/mwsym.2001.966991

Abstract

This paper presents a programmable phase-locked-loop (PLL)-based fractional-N frequency synthesizer that uses a third-order /spl Delta//spl Sigma/-modulator. The in-band phase noise of -97 dBc/Hz in the integer-mode and -94 dBc/Hz in the fractional-mode is measured at 30 kHz offset. In addition to offering an ultra-fine frequency resolution of down to 12.4 Hz and very low in-band phase noise this frequency synthesizer offers, with a loop-bandwidth of about 100 kHz, a very fast settling time of less than 95 /spl mu/s when a 75 MHz jump is applied. This feature enables multiple RF applications, including GSM to send a signal and quickly reset to send another signal to meet high data throughput requirements.

Keywords

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