Formal validation of virtual finite state machines
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 6 references indexed in Scilit:
- Protocol verification as a hardware design aidPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- VFSM executable specificationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A partial approach to model checkingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Symbolic model checking: 10/sup 20/ states and beyondPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Combining partial order reductions with on-the-fly model-checkingPublished by Springer Nature ,1994
- Formal Methods at AT&T - An Industrial Usage ReportPublished by Elsevier ,1992