Impact of the gate-drain overlapped device (GOLD) for deep submicrometer VLSI
- 1 January 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 35 (12) , 2088-2093
- https://doi.org/10.1109/16.8781
Abstract
No abstract availableKeywords
This publication has 8 references indexed in Scilit:
- The impact of N-drain length and gate—drain/source overlap on submicrometer LDD devices for VLSIIEEE Electron Device Letters, 1987
- The impact of gate-drain overlapped LDD (GOLD) for deep submicron VLSI'sPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- A novel submicron LDD transistor with inverse-T gate structurePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- The effects of weak gate-to-drain(source) overlap on MOSFET characteristicsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- Structure-enhanced MOSFET degradation due to hot-electron injectionIEEE Electron Device Letters, 1984
- An As-P(n+-n-)double diffused drain MOSFET for VLSI'sIEEE Transactions on Electron Devices, 1983
- Intermediate Oxide Formation in Double‐Polysilicon Gate MOS StructureJournal of the Electrochemical Society, 1980
- Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistorIEEE Transactions on Electron Devices, 1980