Noise-generation analysis and noise-suppression design techniques in megabit DRAMs
- 1 August 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 22 (4) , 619-622
- https://doi.org/10.1109/jssc.1987.1052782
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- An experimental 4Mb CMOS DRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- A 1-Mbit CMOS DRAM with fast page mode and static column modeIEEE Journal of Solid-State Circuits, 1985
- Half-V/SUB DD/ bit-line sensing scheme in CMOS DRAMsIEEE Journal of Solid-State Circuits, 1984
- A low-power sub 100 ns 256K bit dynamic RAMIEEE Journal of Solid-State Circuits, 1983
- A high-speed 16-kbit n-MOS random-access memoryIEEE Journal of Solid-State Circuits, 1976