High-speed GaAs SCFL monolithic integrated decision circuit for Gbit/s optical repeaters
- 10 November 1983
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 19 (23) , 983-985
- https://doi.org/10.1049/el:19830668
Abstract
A high-speed GaAs monolithic integrated decision circuit for Gbit/s optical repeaters, based on source coupled FET logic (SCFL) and designed to be completely ECL-compatible, has been developed. A clock phase margin of 150 degrees at 2 Gbit/s and IC yields of about 60% are achieved by using SCFL configuration. The developed IC operates stably from 10 to 60°C ambient temperature over a supply voltage fluctuation of more than 2 V.Keywords
This publication has 2 references indexed in Scilit:
- A GaAs High-Speed Counter Using Current Mode LogicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- GaAs logic for multi-Gb data generatorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982