A GaAs High-Speed Counter Using Current Mode Logic

23 March 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 83, 12-16
https://doi.org/10.1109/mcs.1983.1151032

Abstract

A single-clocked divide-by-four counter with maximum operating frequency of 3.4 GHz has been developed. The circuit was fabricated using a tungsten-silicide gate self-alignment technique with full ion implantation. The basic building block of the counter current mode logic (CML) master-slave flip-flop similar to Si ECL.

Keywords

GALLIUM ARSENIDE
COUNTING CIRCUITS
LOGIC
FETS
THRESHOLD VOLTAGE
RESISTORS
DRIVER CIRCUITS
FLIP-FLOPS
CLOCKS
COUPLING CIRCUITS

This publication has 1 reference indexed in Scilit:

A GaAs 1K static RAM using tungsten silicide gate self-aligned technology
IEEE Journal of Solid-State Circuits, 1983