A user configurable gate array using CMOS-EPROM technology

4 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 31.7/1-31.7/4
https://doi.org/10.1109/CICC.1990.124846

Abstract

A 68-pin programmable gate array, implemented in 1- mu m CMOS-EPROM technology, is described. Input-to-output delay of 20 ns for single-level logic is achieved for an array of 258 input lines X 199 product terms. Architecture with 96 NAND foldbacks allows multilevel logic capability. The die size is 55.3 Kmil/sup 2/, and a power-down option is provided. In addition to the main array there is a clock array which generates 10 internal clocks for 10 of the buried JK flip-flops. A scan mode is implemented to offer additional testability of the flip-flops.<>

Keywords

CMOS TECHNOLOGY
CIRCUIT TESTING
PROGRAMMABLE LOGIC ARRAYS
FLIP-FLOPS
LOGIC TESTING
CMOS LOGIC CIRCUITS
LOGIC DEVICES
LOGIC ARRAYS
PROGRAMMABLE LOGIC DEVICES
CLOCKS

This publication has 1 reference indexed in Scilit:

A 16ns CMOS EEPLA with reprogrammable architecture
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1986