A graph-based simplex algorithm for minimizing the layout size and the delay on timing critical paths
- 1 January 1993
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- Layout compaction with minimized delay bound on timing critical pathsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Critical net routingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A hierarchy preserving hierarchical compactorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An Algorithm to Compact a VLSI Symbolic Layout with Mixed ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983