A 5 GHz, 32 mW CMOS frequency synthesizer with an injection locked frequency divider
- 20 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A fully integrated 5 GHz phase locked loop- (PLL-) based frequency synthesizer is designed in a 0.24 /spl mu/m CMOS technology. A voltage-controlled differential injection-locked frequency divider (VCDILFD) is used as the first frequency divider in the PLL feedback loop to reduce power consumption and eliminate the need for an off-chip frequency divider. The total synthesizer power consumption is 32 mW. The phase noise is measured to be -101 dBc/Hz at 1 MHz offset frequency. The PLL bandwidth is 300 kHz and the measured spurious level at the adjacent channel is less than -54 dBc.Keywords
This publication has 6 references indexed in Scilit:
- A physical model for planar spiral inductors on siliconPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Superharmonic injection locked oscillators as low power frequency dividersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Analysis and optimization of accumulation-mode varactor for RF ICsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Superharmonic injection-locked frequency dividersIEEE Journal of Solid-State Circuits, 1999
- Simple accurate expressions for planar spiral inductancesIEEE Journal of Solid-State Circuits, 1999
- On-chip Spiral Inductors With Patterned Ground Shields For Si-based RF IC'sPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1997