Chrominance/luminance signal separation and syntheses chips developed with a DSP silicon compiler
- 1 June 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems for Video Technology
- Vol. 2 (2) , 245-254
- https://doi.org/10.1109/76.143423
Abstract
VLSI chips for luminance/chrominance (Y/C) signal separation and synthesis have been developed. Application-specific FIR filter structures and canonical signed-digit representation (CSR) multipliers used in the filters make it possible to develop compact high-speed VLSI chips. A silicon compiler, which employs the optimal FIR filter structures and supplies the optimal filter design faculty, has contributed to quick VLSI development. Y/C signal separation using four video FIR filters and Y/C signal synthesis using three video FIR filters are implemented on single chips by 1.2-μm CMOS technologyKeywords
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