New techniques for deterministic test pattern generation
- 27 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 16 references indexed in Scilit:
- Combinational profiles of sequential benchmark circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- ATPG for ultra-large structured designsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Robust search algorithms for test pattern generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Combinational test generation using satisfiabilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1996
- Dynamic search-space pruning techniques in path sensitizationPublished by Association for Computing Machinery (ACM) ,1994
- Test pattern generation using Boolean satisfiabilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- PROOFS: a fast, memory-efficient sequential circuit fault simulatorIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- Improved deterministic test pattern generation with applications to redundancy identificationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- SOCRATES: a highly efficient automatic test pattern generation systemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- The Complexity of Fault Detection Problems for Combinational Logic CircuitsIEEE Transactions on Computers, 1982