Abstract
Fault tolerant memory mechanizations are presented in this paper which combine standard Error Detection and Correction (EDAC) techniques with unique memory electrical/spacial organizations and computer protocols which account for single particle radiation effects and significantly reduce their impact on the memory system. The mechanizations also enhance reliability and increase survivability to macroscopic radiation effects including total dose failure and dose rate upset. Standard EDAC mechanizations allow the memory designer to reduce susceptibility to single particle soft upsets at the system level by orders of magnitude. The memory organization and computer protocols presented herein extend this susceptibility reduction to latchup and multiple soft or hard errors in a common word. The mechanizations are compatible with implementation on auxiliary LSI chip sets or partially in VHSIC RAM device structures themselves. They are also compatible with fault tolerant computer mechanizations which account for failure or upset of non RAM device logic circuitry (Processor and Memory).

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