Design techniques for low-voltage high-speed digital bipolar circuits
- 1 March 1994
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 29 (3) , 332-339
- https://doi.org/10.1109/4.278358
Abstract
No abstract availableThis publication has 7 references indexed in Scilit:
- Physical limitations on frequency and power parameters of transistorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A 6 GHz 60 mW BiCMOS phase-locked loop with 2 V supplyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- BEST: a BiCMOS-compatible super-self aligned ECL technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 1-GHz/0.9-mW CMOS/SIMOX divide-by-128/129 dual-modulus prescaler using a divide-by-2/3 synchronous counterIEEE Journal of Solid-State Circuits, 1993
- Low-voltage ULSI designIEEE Journal of Solid-State Circuits, 1993
- A 1.5-V full-swing BiCMOS logic circuitIEEE Journal of Solid-State Circuits, 1992
- An 8-b 800-MHz DACIEEE Journal of Solid-State Circuits, 1990