VLSI considerations for TESH: a new hierarchical interconnection network for 3-D integration
- 1 September 1998
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 6 (3) , 346-353
- https://doi.org/10.1109/92.711306
Abstract
This paper discusses very large scale integration (VLSI) issues, including reconfiguration and yield, for a new interconnection network, "Tori connected mESHes (TESH)". Its key features are the following: (1) it is hierarchical, thus allowing exploitation of computation locality as well as easy expansion up to a million processors, (2) it permits efficient VLSI/ULSI (ultralarge scale integration) realization, and (3) it appears to be well suited for three-dimensional (3-D) implementation. This is due in part to the fact that it requires far fewer number of vertical wires than most other multicomputer networks of comparable diameter, as demonstrated by a 4096 node example. Presented in the paper are the architecture of the new network, node addressing and message routing, VLSI considerations, and most importantly, the reconfiguration and yield studies.Keywords
This publication has 12 references indexed in Scilit:
- The 3-D computerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Interconnection networks with fault-tolerance propertiesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- The emergence of stacked 3D silicon and its impact on microelectronics systems integrationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Data manipulator network for WSI designsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Rapid prototyping of parallel processing systems on TESH networkPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Three-dimensional integration technology for real time micro-vision systemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A hierarchical redundant cube-connected cycle for WSI yield enhancementPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Performance analysis of k-ary n-cube interconnection networksIEEE Transactions on Computers, 1990
- Three-Dimensional VLSIJournal of the ACM, 1983
- The cube-connected cycles: a versatile network for parallel computationCommunications of the ACM, 1981